In, for example, a NAND flash memory, page addresses are set to a plurality of memory cells simultaneously selected by a word line, and data is accessed in units of pages. Accordingly, when data is to be written to the NAND flash memory, parity data is generated for data in a page, and the parity data is written to a page identical to the data. Further, when data is to be read from the NAND flash memory, the parity data is read together with the data in the page, and an error of the data can be corrected by using the parity data. In this way, the user data and parity data are managed in the page, and hence the parity area which can be secured in the page is limited, whereby the error correction capability is restrained. Accordingly, improvement in the error correction capability of the NAND flash memory is desired.